18-bit 3.3v registered buffer integrated circuit systems, inc. ics162834 advance information 0774?02/10/03 recommended applications: pc133 registered memory module pc motherboards servers and workstations provides complete pc133 dimm solution with icsvf2509, icsvf2510 pll. product features: meets jesd 82-2 specification internal series resistors to reduce switching noise 12 ma device capability low voltage operation - v dd = 3.3 0.3v 0.50 mm pitch, 56-pin tssop package 18-bit 3.3v registered buffer function table 1 block diagram notes: 1. h = high voltage level l = low voltage level x = don't care z = high-impedance = low-to-high transition 2. output level before the indicated steady-state input conditions were established, provided that clk is high before le# went low. 3. output level before the indicated steady-state input conditions were established. s t u p n is t u p t u o # e o# e lk l cx ax y hx xx z llxl l llxh h lh ll lh hh lhhxy 0 ) 2 ( lhlxy 0 ) 3 ( pin configurations 56-pin tssop 6.10 mm. body, 0.50 mm. pitch advance information documents contain information on products in the formative or design phase development. characteristic data and other specific ations are design goals. ics reserves the right to change or discontinue these products without notice. third party brands and names are the property of their respective owners. pin description s e m a n n i pn o i t p i r c s e d # e o) w o l e v i t c a ( t u p n i e l b a n e t u p t u o k l ct u p n i k c o l c # e lt u p n i e l b a n e h c t a l x at u p n i a t a d x ys t u p t u o a t a d v d d e g a t l o v y l p p u s d n gd n u o r g 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ics162834 nc nc y1 gnd y2 y3 vdd y4 y5 y6 gnd y7 y8 y9 y10 y11 y12 gnd y13 y14 y15 vdd y16 y17 gnd y18 oe# le# gnd nc a1 gnd a2 a3 vdd a4 a5 a6 gnd a7 a8 a9 a10 a11 a12 gnd a13 a14 a15 vdd a16 a17 gnd a18 clk gnd oe# clk a1 le# to 17 other channels c1 1d ck y1 idt? / ics? 18-bit 3.3v registered buffer ics162834 1 data sheet ics162834
idt? / ics? 18-bit 3.3v registered buffer ics162834 2 ics162834 18-bit 3.3v registered buffer tsd 2 ics162834 advance information 0774?02/10/03 general description the ics162834 low voltage 18-bit register combines d-type latches and d-type flip-flops to allow data flow in transparent, latched and clocked modes. date flow is controlled by output-enable (oe#), latch enable (le#), and clock (clk) inputs. the device operates in transparent mode when le# is held low. the device operates in clocked mode when le# is high and clk is toggled. data transfers from the inputs (a[18:1]) to outputs (y[18:1]) on a positive edge transition of the clock. when oe# is low, the output state is enabled. when oe# is high, the output port is in a high impedance state. the 18-bit registered buffer is designed to operate with a 3.0v to 4.6v supply voltage. all inputs support operation with standard lvttl interface levels. this includes data inputs, clock inputs and control inputs. device outputs meet the requirements of the pc133 registered dimm specification. the device functions as defined supports latched, registered and flow through modes of operations. the pc133 specification requires only registered mode. package is a 56 thin shrink small-outline package as defined by jedec publication, jep95, mo-153.
idt? / ics? 18-bit 3.3v registered buffer ics162834 3 ics162834 18-bit 3.3v registered buffer tsd 3 ics162834 advance information 0774?02/10/03 absolute maximum ratings storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to + 150c supply voltage (v dd ) . . . . . . . . . . . . . . . . . . . -0.5 to 4.6v input voltage (v i ) . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.6v output voltage (v o ) . . . . . . . . . . . . . . . . . . . . -0.5 to v ddq + 0.5 input clamp current (i ik ) . . . . . . . . . . . . . . . . 50 ma output clamp current (i ok ) . . . . . . . . . . . . . . 50 ma continuous output current (i o ) . . . . . . . . . . . 50 ma v dd , v ddq or gnd current/pin . . . . . . . . . . . 100 ma package thermal impedance , o ja . . . . . . . . . . . 64c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. recommended operating conditions parameter min typ max v d d 3.0 3.3 3.6 v in -0.3 3.6 0v d d 0v d d t a 070 v out voltage applied to output or i/o pins outputs enabled outputs high-z description supply voltage voltage applied to input pins operating free-air temperature switching characteristics min max t plh , t phl propagation delay clk to yx 1.8 3.5 ns t sk ( 0 ) output skew* - 500 ps f clock 150 - mhz symbol v cc = 3.3v 0.15v units parameter * skew between any two putputs of the same package and switching in the same direction
idt? / ics? 18-bit 3.3v registered buffer ics162834 4 ics162834 18-bit 3.3v registered buffer tsd 4 ics162834 advance information 0774?02/10/03 electrical characteristics - dc t a = 0 - 70 c; v dd = 3.3 0.3v, v ddq =3.3 0.3v; (unless otherwise stated) symbol parameters conditions v dd (v) min typ max units v ih high-level input voltage 3.0 - 3.6 2.0 v v il low-level input voltage 3.0 - 3.6 0.8 v v oh high-level output voltage i oh = -12 ma, v ih = 2.0v 3.0 2.2 v v ol low-level output voltage i ol = 12 ma, v il = 0.8v 3.0 0.8 i i input leakage current v i = v dd or gnd 3.0 - 3.6 10 a i o z off-state leakage current v o = v dd or gnd#, oe = v dd 20 a i dd quiescent supply current v i = v dd or gnd, i o = 0 40 a * parameters are characterized over recommended operating conditions. critical register specifications* symbol parameters condition v dd (v) min typ max units t p d ** propagation delay (ck to y) r l = 500 ? , c l = 50 pf 3.0 - 3.6 1.4 3.5 ns t p d ** propa g ation dela y (ck to y) r l = 500 ? , c l = 30 pf 3.0 - 3.6 0.7 2.5 ns t s setup time (a before ck) 3.0 - 3.6 1.0 ns t h hold time (a after ck) 3.0 - 3.6 0.6 ns c i clock input capacitance 3.0 - 3.6 3.3 4.0 6.0 pf * parameters are characterized over recommended operating conditions. ** the t pd value in this table would equate to the 'time-to-vm' delay described in the post register timing specifications of the pc133 registered dimm specification. the first value applies to dimms with nine sdram loads per register output, and the second to dimms with eighteen sdram loads per register output. these values should serve as only an initial starting point,
5 ics162834 advance information 0774?02/10/03 d e t s e t r e t e m a r a pn o i t i s o p h c t i w s t h l p n e p o t l h p n e p o t h z p d n g t l z p v x 2 d d t z h p d n g t z l p v x 2 d d dut r l c l r l 2 x v dd open gnd puls e generator r t test circuit component values: r l = load resistor = 500 ? c l = load capacitance and includes probe and jig capacitance r t = termination resistance should be equal to z out of pulse generator v in = 0 to v dd t r = t f 2.0 ns (10% to 90%) unless otherwise specified. test circuit test circuit and switching waveforms idt? / ics? 18-bit 3.3v registered buffer ics162834 5 ics162834 18-bit 3.3v registered buffer tsd
idt? / ics? 18-bit 3.3v registered buffer ics162834 6 ics162834 18-bit 3.3v registered buffer tsd 6 ics162834 advance information 0774?02/10/03 5 inpu t v ih 0v v oh v ol t plh1 t sk (x) output 1 output 2 t phl1 t sk (x) t plh2 t phl2 v t v t v oh v t v ol t sk (x) = t plh2 - t plh1 or t phl2 - t phl 1 low-high-low pulse high-low-high puls e v t t w v t control inpu t t pl z 0v output normally lo w t pz h 0v switch closed output normally high enable disable switch open t phz 0v v lz v oh v t v t t pzl v load/2 v load/2 v ih v t v ol v hz notes: switching waveforms 1. for t sk (o) output1 and output2 are any two outputs. 2. for t sk (b) output1 and output2 are in the same bank. enable and disable times output skew - t sk(x) note: 1. diagram shown for input control enable-low and input control disable-high. pulse width a n ck y n t pl h t ph l v ih v il v ih v il v oh v ol a n ck y n t s t s v ih v ih v il v ih v il v oh v ol a n ck y n t h t h v ih v il v ih v il v oh v ol hold time measurements propagation delay measurement setup time measurements
ics162834 18-bit 3.3v registered buffer tsd 7 ics162834 advance information 0774?02/10/03 ordering information ICS162834AG-T designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) package type g = tssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y g - ppp - t index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (0.020 mil) min max min max a--1.20--.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 v ariations min max min max 56 13.90 14.10 .547 .555 10-0039 n d mm. d (inch) ref er ence do c.: jedec pub licat io n 9 5, m o- 153 0.50 basic 0.020 basic see variations see variations see variations see variations 8.10 basic 0.319 basic symbol in millimeters in inches common dimensions common dimensions idt? / ics? 18-bit 3.3v registered buffer ics162834 7
ics162834 18-bit 3.3v registered buffer tsd ics650-40a ethernet switch clock source tsd ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa xx-xxxx-xxxxx corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support clockhelp@idt.com 408-284-8200 innovate with idt and accelerate your future networks. contact: www.idt.com ics252 field programmable dual output ss versaclock synthesizer tsd
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